CAPCON

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Interpret as CAPCON

Description

Capture Control read address

Fields

CAP0MCI0_RE	A 1 in this bit enables a channel 0 capture event on a rising edge on MCI0.
CAP0MCI0_FE	A 1 in this bit enables a channel 0 capture event on a falling edge on MCI0.
CAP0MCI1_RE	A 1 in this bit enables a channel 0 capture event on a rising edge on MCI1.
CAP0MCI1_FE	A 1 in this bit enables a channel 0 capture event on a falling edge on MCI1.
CAP0MCI2_RE	A 1 in this bit enables a channel 0 capture event on a rising edge on MCI2.
CAP0MCI2_FE	A 1 in this bit enables a channel 0 capture event on a falling edge on MCI2.
CAP1MCI0_RE	A 1 in this bit enables a channel 1 capture event on a rising edge on MCI0.
CAP1MCI0_FE	A 1 in this bit enables a channel 1 capture event on a falling edge on MCI0.
CAP1MCI1_RE	A 1 in this bit enables a channel 1 capture event on a rising edge on MCI1.
CAP1MCI1_FE	A 1 in this bit enables a channel 1 capture event on a falling edge on MCI1.
CAP1MCI2_RE	A 1 in this bit enables a channel 1 capture event on a rising edge on MCI2.
CAP1MCI2_FE	A 1 in this bit enables a channel 1 capture event on a falling edge on MCI2.
CAP2MCI0_RE	A 1 in this bit enables a channel 2 capture event on a rising edge on MCI0.
CAP2MCI0_FE	A 1 in this bit enables a channel 2 capture event on a falling edge on MCI0.
CAP2MCI1_RE	A 1 in this bit enables a channel 2 capture event on a rising edge on MCI1.
CAP2MCI1_FE	A 1 in this bit enables a channel 2 capture event on a falling edge on MCI1.
CAP2MCI2_RE	A 1 in this bit enables a channel 2 capture event on a rising edge on MCI2.
CAP2MCI2_FE	A 1 in this bit enables a channel 2 capture event on a falling edge on MCI2.
RT0	If this bit is 1, TC0 is reset by a channel 0 capture event.
RT1	If this bit is 1, TC1 is reset by a channel 1 capture event.
RT2	If this bit is 1, TC2 is reset by a channel 2 capture event.
RESERVED	Reserved.

Links

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